Semiconductor processing includes deposition processes such as chemical vapor deposition (CVD) of metal, dielectric and semiconducting materials, etching of such layers, ashing of photoresist masking layers, etc. Such semiconductor processes are typically carried out in vacuum chambers wherein process gas is used to treat a substrate such as a semiconductor wafer, flat panel display substrate, etc. The process gas can be supplied to the interior of the vacuum chamber by a gas distribution system such as a showerhead, a gas distribution ring, gas injectors, etc. Reactors having plural gas distribution systems are disclosed in U.S. Pat. Nos. 5,134,965; 5,415,728; 5,522,934; 5,614,055; 5,772,771; 6,013,155; and 6,042,687.
In the case of etching, plasma etching is conventionally used to etch metal, dielectric and semiconducting materials. A plasma etch reactor typically includes a pedestal supporting the silicon wafer on a bottom electrode, an energy source which energizes process gas into a plasma state, and a process gas source supplying process gas to the chamber.
A common requirement in integrated circuit fabrication is the etching of openings such as contacts and vias in dielectric materials. The dielectric materials include doped silicon oxide such as fluorinated silicon oxide (FSG), undoped silicon oxide such as silicon dioxide, silicate glasses such as boron phosphate silicate glass (BPSG) and phosphate silicate glass (PSG), doped or undoped thermally grown silicon oxide, doped or undoped TEOS deposited silicon oxide, etc. The dielectric dopants include boron, phosphorus and/or arsenic. The dielectric can overlie a conductive or semiconductive layer such as polycrystalline silicon, metals such as aluminum, copper, titanium, tungsten, molybdenum or alloys thereof, nitrides such as titanium nitride, metal silicides such as titanium silicide, cobalt silicide, tungsten silicide, molybdenum silicide, etc. A plasma etching technique, wherein a parallel plate plasma reactor is used for etching openings in silicon oxide, is disclosed in U.S. Pat. No. 5,013,398.
U.S. Pat. No. 5,736,457 describes single and dual “damascene” metallization processes. In the “single damascene” approach, vias and conductors are formed in separate steps wherein a metallization pattern for either conductors or vias is etched into a dielectric layer, a metal layer is filled into the etched grooves or via holes in the dielectric layer, and the excess metal is removed by chemical mechanical planarization (CMP) or by an etch back process. In the “dual damascene” approach, the metallization patterns for the vias and conductors are etched in a dielectric layer and the etched grooves and via openings are filled with metal in a single metal filling and excess metal removal process.
Various methods in semiconductor processing, such as damascene metallization processes, require methods for removing organic material over substrates, such as stripping a photoresist mask, etching an organic bottom antireflective coating (BARC), removing a via plug, or etching an organic dielectric layer.